DFT Lead

CDI à 100% de suite ou à convenir.
Postulation uniquement en ligne - merci de mentionner sous source (ORP)

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a resourceful DFT Lead based in Lausanne, Switzerland.

Key Responsibilities:

Lead DFT activity for the next generation products
Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes, DDR, PCIe designs
Closely working with Physical implementation team to define timing constraints in test modes and helping to converge for successful tapeout
Good understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development
Define the test plan by closely working with the teams and drive the pattern development of functional/structural tests for final/wafer test program
Closely working with the teams to bring up device qualification solution for HTOL
Drive lab bench silicon debug to understand ATE bring up issues

Skills:

Excellent communication skills, and strong team player with can do type of attitude
Mentoring the team members
Excellent debugging skills
Good scripting skills to develop automation

Qualifications:

12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation
Proven track record of delivering DFT solution to complex designs
Experience working with IJTAG methodologies
Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
Strong debug capabilities in simulating patterns with timing
Experience in defining test mode constraints and analyzing the timing reports
Experience with industry standard EDA tools for DFT, timing, and simulation
Good knowledge of System Verilog
Experience with chiplet based designs is a plus

Education:

Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)

If this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/