Formal Verification Engineer CH, UK, DE, DK

CDI à 100% de suite ou à convenir.
Postulation uniquement en ligne - merci de mentionner sous source (ORP)

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a resourceful Formal Verification Engineer, based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark.

Key Responsibilities

Develop formal verification methodologies and best practices
Participate in RTL design reviews
Prepare design verification plan based on design specifications
Document results and coverage metrics for formal sign-off
Plan and schedule assigned projects for timely completion
Maintain design verification environment and track & close design bugs

Skills

Must possess great communication skills, rigorous with an analytical mind and be a strong team player
Good scripting techniques (python, Perl or TCL for automation), regression setup & management
Deep understanding of Formal Verification technologies
Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure)
Proficiency in temporal logic assertion-based languages such as SVA or PSL.
Knowledge of traditional simulation-based verification methodologies (a plus)
Excellent analytical, problem-solving and debugging skills
Strong understanding of instruction-set architectures, interrupt handling and bus architectures
Knowledge of Cadence JasperGold and VManager is preferrable

Experience

5+ years’ experience in the semiconductor industry
Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC
Skilled in trade-offs between quality and schedule
Working with RTL design engineers to develop a formal micro-architecture specification
Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
Delivered reusable and optimized formal models and verification codebases to improve efficiency across project

Education

Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/