Mixed Signal Verification Engineer CH, UK, DE, DK
- Entreprise
- Kandou Bus SA
- Lieu
- St-Sulpice VD
- Date de publication
- 08.01.2026
- Référence
- 5078750
Description
hallenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a resourceful Mixed Signal Verification Engineer, based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark.
Key Responsibilities
Verification plan tasks in analog/mixed signal environment related to high speed SerDes designs
Debug and flag bugs with design team
Enhance and develop new methodologies with the verification team and EDA vendors
Document and track verification plan tasks, bug findings and methodology work
Skills
Good scripting techniques
Good understanding of fabrication process, process corners, simulation, and verification setup
Very good knowledge on electrical and discrete test benches / solvers in terms of run time optimization
Very good knowledge about simulation tools and debugging techniques
Good understanding of revision control
Good communication and reporting skills
Experience
At least 10 years of experience on digital/mixed signal/analog verification: test bench design, connect modules, design electrical/discrete partitioning, UDN, wreal, compile and elaboration debug
Experience in behavioral modelling, basic knowledge of analog building blocks
Experience with simulator: fast analog solver e.g., Cadence APS, SpectreX / digital solver e.g., Cadence Xcelium
Experience in constrained random testbench development
Experience in System Verilog Assertions
Experience with Cadence Ocean Script
Experience with Cadence Virtuoso Framework: Schematic editor, Assembler, AMS
Experience on high-speed communication systems such as SerDes would be a plus
Good digital verification background with some Specman/SV UVM exposure and/or analog verification background
Education
Graduated in Electrical Engineering
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !
Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/